Tyler Sorensen

Tyler Sorensen

Principal Researcher

Microsoft Research (RiSE)

Associate Professor (on leave), UC Santa Cruz

About

I am a Principal Researcher in the RiSE group at Microsoft Research, and an Associate Professor (on leave) at UC Santa Cruz. My research focuses on concurrency: programming, modeling, testing, and architecture, with the goal of enabling correct and efficient applications on emerging architectures. I explore these ideas primarily through GPGPU programming.

Previously, I was a postdoc at Princeton with Margaret Martonosi and received my PhD from Imperial College London advised by Alastair Donaldson.

πŸ“’ News

  • 2026: Parallel X accepted to SIGCSE 2026!
  • 2025: BetterTogether wins Best Paper Award at IISWC 2025!

PhD Students

Agentic Workflows

I am experimenting with agentic workflows. Enjoy!

Did You Know? (daily fact mined from my papers)

Did you know? Traditional simultaneous multithreading (SMT) designs must choose between out-of-order (OoO) threads (for instruction-level parallelism) or in-order (InO) threads (for thread-level parallelism) β€” but SHADOW is the first CPU architecture to run both kinds of threads concurrently on the same core, dynamically stealing work between them. On memory-bound sparse workloads like those found in deep learning and graph processing, SHADOW achieves up to 3.16Γ— speedup and 1.33Γ— average improvement over a standard OoO CPU, with only 1% area and power overhead. (from: SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads)

Research Idea (daily idea mined from my papers and related works on arXiv)

Placeholder: check back soon β€” an agent will populate this with a research idea inspired by my papers and recent arXiv publications.

Publications

All papers are provided in full markdown and summary markdown formats to make them easier for agents and LLMs to process. See the [Markdown Full] and [Markdown Summary] links next to each paper, or browse the combined index.

Papers

2026 (2 papers)
Memory DisOrder: Memory Re-orderings as a Timerless Side-channel S. Siddens, S. Srivastava, R. Levine, J. Dykstra, T. Sorensen ArXiv, 2026 [PDF] [Markdown Full] [Markdown Summary]
Parallel X: Redesigning of a Parallel Programming Educational Game with Semantic Foundations and Transfer Learning D. McKee, Z. Lin, B. Fox, J. Li, J. Zhu, M. Seif El-Nasr, T. Sorensen SIGCSE, 2026 [PDF] [Markdown Full] [Markdown Summary]
2025 (5 papers)
SafeRace: Assessing and Addressing WebGPU Memory Safety in the Presence of Data Races R. Levine, A. Lee, N. Abbas, K. Little, T. Sorensen OOPSLA, 2025 [PDF] [Markdown Full] [Markdown Summary]
SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads I. Chaturvedi, B. R. Godala, T. Sorensen, A. Gangavaram, T. M. Aamodt, D. Flyer, D. I. August MICRO, 2025 [PDF] [Markdown Full] [Markdown Summary]
PEAK: A Performance Engineering AI-Assistant for GPU Kernels Powered by Natural Language Transformation M. U. Tariq, A. Jangda, A. Moreira, M. Musuvathi, T. Sorensen ArXiv, 2025 [PDF] [Markdown Full] [Markdown Summary]
BetterTogether: An Interference-Aware Framework for Fine-grained Software Pipelining on Heterogeneous SoCs Y. Xu, R. Sharma, Z. Chen, S. Mistry, T. Sorensen IISWC, 2025 πŸ† Best Paper Award [PDF] [Markdown Full] [Markdown Summary]
miniGiraffe: A Pangenomic Mapping Proxy App J. I. Dagostini, J. B. Manzano, T. Sorensen, S. Beamer IISWC, 2025 [PDF] [Markdown Full] [Markdown Summary]
2024 (3 papers)
GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction I. Chaturvedi, B. R. Godala, Y. Wu, Z. Xu, K. Iliakis, P.-E. Eleftherakis, S. Xydis, D. Soudris, T. Sorensen, S. Campanoni, T. M. Aamodt, D. I. August ISCA, 2024 [PDF] [Markdown Full] [Markdown Summary]
Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics Implementations L. Geeson, J. Brotherston, W. Dijkstra, A. F. Donaldson, L. Smith, T. Sorensen, J. Wickerson OOPSLA, 2024 [PDF] [Markdown Full] [Markdown Summary]
LeftoverLocals: Listening to LLM Responses Through Leaked GPU Local Memory T. Sorensen, H. Khlaaf ArXiv, 2024 [PDF] [Slides] [Blog] [Wired Article] [Markdown Full] [Markdown Summary]
2023 (3 papers)
GPUHarbor: Testing GPU Memory Consistency at Large (Experience Paper) R. Levine, M. Cho, D. McKee, A. Quinn, T. Sorensen ISSTA, 2023 πŸ† Distinguished Artifact Award [PDF] [Markdown Full] [Markdown Summary]
MC Mutants: Evaluating and Improving Testing for Memory Consistency Specifications R. Levine, T. Guo, M. Cho, A. Baker, R. Levien, D. Neto, A. Quinn, T. Sorensen ASPLOS, 2023 πŸ† Distinguished Paper Award, Distinguished Artifact Award [PDF] [Markdown Full] [Markdown Summary]
Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads Y. Xu, A. Li, T. Sorensen ISPASS, 2023 [PDF] [Markdown Full] [Markdown Summary]
2021 (3 papers)
Specifying and Testing GPU Workgroup Progress Models T. Sorensen, L. F. Salvador, H. Raval, H. Evrard, J. Wickerson, M. Martonosi, A. F. Donaldson OOPSLA, 2021 [PDF] [Code] [Test Explorer] [Markdown Full] [Markdown Summary]
The Semantics of Shared Memory in Intel CPU/FPGA Systems D. Iorga, A. F. Donaldson, T. Sorensen, J. Wickerson OOPSLA, 2021 [PDF] [Code] [Blog] [Markdown Full] [Markdown Summary]
GraphAttack: Optimizing Data Supply for Graph Applications on In-Order Multicore Architectures A. Manocha, T. Sorensen, E. Tureci, O. Mathews, J. L. AragΓ³n, M. Martonosi TACO, 2021 [PDF] [Markdown Full] [Markdown Summary]
2020 (3 papers)
Foundations of Empirical Memory Consistency Testing J. Kirkham, T. Sorensen, E. Tureci, M. Martonosi OOPSLA, 2020 [PDF] [Video] [Markdown Full] [Markdown Summary]
Slow and Steady: Measuring and Tuning Multicore Interference D. Iorga, T. Sorensen, J. Wickerson, A. F. Donaldson RTAS, 2020 [PDF] [Markdown Full] [Markdown Summary]
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems O. Matthews, A. Manocha, D. Giri, M. Orenes-Vera, E. Tureci, T. Sorensen, T. Ham, J. L. AragΓ³n, L. Carloni, M. Martonosi ISPASS, 2020 πŸ† Best Paper Nomination [PDF] [Markdown Full] [Markdown Summary]
2019 (1 paper)
One size doesn't fit all: quantifying performance portability of graph applications on GPUs T. Sorensen, S. Pai, A. F. Donaldson IISWC, 2019 πŸ† Best Paper Award [PDF] [Slides] [Markdown Full] [Markdown Summary]
2018 (2 papers)
GPU schedulers: how fair is fair enough? T. Sorensen, H. Evrard, A. F. Donaldson CONCUR, 2018 [PDF] [Markdown Full] [Markdown Summary]
The semantics of transactions and weak memory in x86, Power, ARM, and C++ N. Chong, T. Sorensen, J. Wickerson PLDI, 2018 πŸ† Best Paper Award [PDF] [Markdown Full] [Markdown Summary]
2017 (2 papers)
Cooperative kernels: GPU multitasking for blocking algorithms T. Sorensen, H. Evrard, A. F. Donaldson FSE, 2017 πŸ† Distinguished Paper Award [PDF] [Code] [Slides] [Poster] [Markdown Full] [Markdown Summary]
Automatically comparing memory consistency models J. Wickerson, M. Batty, T. Sorensen, G. Constantinides POPL, 2017 [PDF] [Markdown Full] [Markdown Summary]
2016 (2 papers)
Portable inter-workgroup barrier synchronisation for GPUs T. Sorensen, A. F. Donaldson, M. Batty, G. Gopalakrishnan, Z. Rakamaric OOPSLA, 2016 [PDF] [Code] [Markdown Full] [Markdown Summary]
Exposing errors related to weak memory in GPU applications T. Sorensen, A. F. Donaldson PLDI, 2016 [PDF] [Slides] [Video] [Markdown Full] [Markdown Summary]
2015 (1 paper)
GPU concurrency: weak behaviours and programming assumptions J. Alglave, M. Batty, A. F. Donaldson, G. Gopalakrishnan, J. Ketema, D. Poetzl, T. Sorensen, J. Wickerson ASPLOS, 2015 [PDF] [Dataset] [Poster] [Markdown Full] [Markdown Summary]

Workshop Papers

Workshop Papers (5)
A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration T. Sorensen, A. Manocha, E. Tureci, M. Orenes-Vera, J. L. AragΓ³n, M. Martonosi ICCAD, 2020 (Invited) [PDF] [Slides] [Markdown Full] [Markdown Summary]
Performance evaluation of OpenCL standard support (and beyond) T. Sorensen, S. Pai, A. F. Donaldson IWOCL, 2019 πŸ† Best Paper Award [PDF] [Slides] [Markdown Full] [Markdown Summary]
The hitchhiker's guide to cross-platform OpenCL application development T. Sorensen, A. F. Donaldson IWOCL, 2016 [PDF] [Slides] [Markdown Full] [Markdown Summary]
I compute, therefore I am (buggy): methodic doubt meets multiprocessors J. Alglave, L. Maranget, D. Poetzl, T. Sorensen TinyToCS, 2015 [PDF] [Markdown Full] [Markdown Summary]
Towards shared memory consistency models for GPUs T. Sorensen, J. Alglave, G. Gopalakrishnan, V. Grover ICS, 2013 πŸ† 1st Place Undergrad SRC [PDF] [Preprint] [Poster] [Markdown Full] [Markdown Summary]

Theses

Theses (3)
Device-wide Barrier Synchronisation on Graphics Processing Units T. Sorensen (Adviser: A. F. Donaldson) PhD Thesis, Imperial College London, 2018 [PDF]
Testing and Exposing Weak GPU Memory Models T. Sorensen (Advisers: G. Gopalakrishnan, Z. Rakamaric) MS Thesis, University of Utah, 2014 [PDF]
Towards Shared Memory Consistency Models for GPUs T. Sorensen (Adviser: G. Gopalakrishnan) BS Thesis, University of Utah, 2012 [PDF]

Teaching

I have taught classes at UCSC on compilers and parallel programming.

Alumni

I've had the privilege of working with the following students at UCSC who have gone on to really great things!

Acknowledgements

I would like to thank various organizations for supporting my work, either through employment, contracting, or research funding: Microsoft, Trail of Bits, NSF, Google, DARPA, and the Khronos Group.